A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method
نویسندگان
چکیده
منابع مشابه
A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method
A packet memory stores packets in internet routers and it requires typically RTT ×C for the buffer space, e.g. several GBytes, where RTT is an average round-trip time of a TCP flow and C is the bandwidth of the router’s output link. It is implemented with DRAM parts which are accessed in parallel to achieve required bandwidth. They consume significant power in a router whose scalability is heav...
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ژورنال
عنوان ژورنال: IEICE Transactions on Information and Systems
سال: 2013
ISSN: 0916-8532,1745-1361
DOI: 10.1587/transinf.e96.d.963